1. Field of the Invention
The present invention relates to nonvolatile semiconductor memory devices which can write, read and erase data electrically.
2. Description of the Related Art
As semiconductor memories, there are a DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), a flash memory, an EEPROM (Electrically Erasable Programmable Read Only Memory) and the like. An EEPROM is used for mobile devices such as digital audio players (DAP), and thus, large capacity, high precision, and low power consumption are important for an EEPROM.
In an EEPROM, it is usual that verify write or verify erase is conducted, which includes an operation for verifying that a state after writing or erasing is in a predetermined range. In particular, in a nonvolatile memory which operates at a low voltage, it is necessary to control a state after writing or erasing with high accuracy and thus, such a verify operation is essential.
In the verify write/erase operation, an operation period in which a fixed period of write/erase operation is conducted, and a read period for verifying that a state after writing or erasing is in a predetermined range are conducted alternately.
FIG. 2 and FIG. 3 show this state. FIG. 2 is a simple block diagram, in which a read circuit 202 and a write/erase circuit 201 are connected to a selected memory cell 203. A verify signal Sv is output from the read circuit 202, and is input to the write/erase circuit 201. The write/erase circuit 201 conducts write/erase in response to the verify signal Sv. FIG. 3 shows a procedure of the verify write/erase. In FIG. 3, the read circuit operates (this state is referred to as “active”) first, so that read is conducted. At that time, the write/erase circuit does not operate (this state is referred to as “not active”). The verify signal Sv output from the read circuit is Low when a state of the memory cell when data is read is different from an intended state, while the verify signal Sv is High when a state of the memory cell when data is read is the same as an intended state. When the verify signal Sv is Low, the write/erase circuit operates (active) after the termination of a read operation, and a fixed period of write/erase operation is conducted. Subsequently, read is conducted again and a state of the memory cell is compared with an intended state. Similarly, when the verify signal Sv is Low, a fixed period of write/erase operation is conducted again. These operations are repeated, and when the verify signal Sv is High, the verify write/erase operation is terminated. In this manner, the verify operation is conducted.
Further, as for EEPROMs, there are various types such as a NOR type, a NAND type and an AND type depending on a structure and a driving method of a memory cell.
In general, a NAND type can increase the integration degree more than a NOR type. This is because in the NAND type, the total number of memory elements and transistors necessary for storing information per one bit can be more reduced. However, in the NAND type, a threshold voltage of a memory element is necessary to be controlled with higher accuracy than the NOR type, and in view of this point, the verify operation is essential (Reference 1: Fujio Masuoka “Rapidly-Advancing Flash Memory (revised new version)”, first edition, May 2003, p. 150 (FIG. 4. 11)).